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Verification Manager

3 Nov 2025
Hyderabad, Telangana, India
Verified by Turrior

Content + Source + Freshness • 17 Dec 2025 • 95% confidence

80 / 100

Offer value

Valuable position due to leadership role over diverse verification projects in a cutting-edge technology environment.

  • Lead a team of verification engineers in a reputable IoT firm.
  • Manage multiple verification projects and schedules.
  • Significant professional development and mentoring opportunities.
  • Requires advanced expertise and management experience.
Pros
  • Strong leadership opportunity in technical verification.
  • Significant influence on project development timelines.
  • Ability to mentor and grow a team of engineers.
Cons
  • High expectations for collaborative communication.
  • Requires substantial management experience (3+ years).
  • Variable workload due to concurrent project management.

Who it's for

Lead / Management • On-site or hybrid potentially

Good fit
  • Experienced verification managers.
  • Leaders eager to guide technical teams.
  • Professionals aiming to expand their roles in engineering management.
Not recommended for
  • Newcomers to the verification engineering field.
  • Candidates uninterested in team leadership or management.
  • Those not comfortable with dynamic project environments.

Motivation fit

Desire to take on a mentoring role in engineering.Motivation to improve team performance and output quality.Interest in overseeing complex verification methodologies.

Key skills

Verification plan developmentTeam management and leadershipKnowledge of System Verilog and UVMProject scheduling and resource allocation
Score: 80/100 AI verified analysis

About the job

Responsibilities:

  • Lead, supervise, mentor, and develop a team of verification engineers across multiple projects. Manage verification team deliverables, quality, schedules, and resource allocation for concurrent projects. (20%)

  • Track & report verification progress using quantitative metrics and coverage analysis. Identify and mitigate verification risks early. Report to remote verification & design teams. Coordinate with project management and cross-functional teams. (20%)

  • Drive definition and implementation of comprehensive verification plans and test strategies for digital/mixed-signal integrated circuit designs. Work closely with design teams to understand micro-architecture and functional specifications. Direct detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (20%)

  • Manage design and implementation of complex testbenches using System Verilog and UVM methodology. Lead block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Improve verification scalability and portability from project to project by environment enhancement and tools automation. Establish and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (20%)

  • Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%)

  • Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%)

  • Technical support to silicon lab evaluation, test, product and application engineers. (5%)

Minimum Qualifications:

  • 8+ years of industry experience in integrated circuit design verification (DV)

  • 3+ years in a technical leadership or management role

  • B.S. or M.S. in Electrical or Computer Engineering

  • Proven track record of successful tape-outs for complex digital or mixed-signal designs

  • Demonstration of ability to lead technical teams and drive high-quality & timely results

  • Experience managing concurrent projects, competing priorities and sub-teams

  • Strong analytical, synthesis and problem solving skills

  • In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals.

  • Proficiency in System Verilog as High-level Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Cadence, Siemens)

  • Experience with standard hardware protocols (I2C, I3C, SPI, MIPI)

  • Independent, self-motivated, rigorous, innovating, team player and able to follow through

  • Excellent verbal and written communication skills

Desired Qualifications

  • Knowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modelling, test and application

  • Experience with analog block behavioral modelling with SV RNM/Verilog/VHDL

  • Experience with consumer and/or ITA market circuit developments

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