Staff Verification Design Engineer
Content + Source + Freshness • 17 Dec 2025 • 95% confidence
Offer value
The analysis aligns with prior roles due to the consistency in skill requirements and company focus.
- Involved in leading-edge technology projects
- Affects product development quality in semiconductor design
- Specific technical skills are highly valued
Pros
- Opportunity to contribute to significant projects in a leading company
- Application of critical technical skills within a collaborative setting
- Exposure to advanced practices in semiconductor verification
Cons
- High expectations for experienced candidates
- Possible high-stakes environment with rigorous demands
- Lack of detailed compensation packages available
Who it's for
Mid to Senior Level • On-site (Hyderabad)
Good fit
- Experienced verification professionals
- Engineers aiming to strengthen their roles in IoT
- Individuals eager to engage in challenging verification tasks
Not recommended for
- Candidates without direct verification experience
- New professionals exploring unrelated careers
- Individuals wanting remote-only opportunities
Motivation fit
Key skills
About the job
Responsibilities:
Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog/mixed-signal (AMS).
Run digital/mixed-signal simulations as well as formal verification.
Work closely with the design team to create verification strategy and detailed verification plan.
Develop tests, run regressions and monitor coverage to ensure tape-out quality.
Participate in design or project reviews and support these with verification perspective and schedule/priority assessment.
Support post-silicon bring-up and debug, for bench validation as well as automated test equipment (ATE) testing.
Improve verification scalability and portability from project to project by environment enhancement and tools automation.
Minimum Qualifications:
3+ years experience in semiconductor industry
M.S. in EE/CS/CE or higher
Hands-on experience with System Verilog as High-level Verification Language and UVM implementation.
Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level.
Scripting experience in Python or Perl.
Clear understanding of ASIC design flow
Solid analytical, synthesis and problem solving skills
Independent, self-motivated, rigorous, team player and able to follow through
Excellent verbal and written communication skills
Desired Qualifications
Experience of setting up UVM verification environment from scratch
Familiarity with VHDL or System Verilog RNM
Automation of verification flow with Python/Perl in industrial setting
Analog behavioral model development/verification experience
