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Careers at Tenstorrent
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SoC Top-Level Physical Design Engineer

$100,000 - $500,000/year
23 Oct 2025
Verified by Turrior

Content + Source + Freshness • 12 Dec 2025 • 95% confidence

85 / 100

Offer value

This position offers excellent compensation and is key to implementing complex AI technology, which is attractive for skilled engineers seeking substantial impact in their work.

  • Competitive salary range: $100k–$500k annually
  • Key role in innovative AI hardware design
  • Opportunities for leadership and interdisciplinary collaboration
Pros
  • Well-compensated role ($100k - $500k) within a growth-focused company
  • Opportunity to work on leading-edge complex AI designs
  • Chance to lead teams and collaborate with multiple disciplines
Cons
  • High demands for expertise in physical design and verification
  • Potential for stressful schedules due to tight deadlines
  • Hybrid work may limit collaboration for some teams

Who it's for

Senior / Lead • Hybrid (Santa Clara, Austin, or Ft. Collins)

Good fit
  • Senior-level engineers in physical design
  • Candidates keen on working within AI technology
  • Individuals with a passion for intricate chip design
Not recommended for
  • New graduates without hands-on design experience
  • Professionals seeking fully remote positions
  • Those who struggle under pressure in fast-paced environments

Motivation fit

Interest in cutting-edge physical design developmentsDesire to influence next-generation AI hardware designMotivation to manage and mentor engineering teams

Key skills

Expertise in full-chip physical designDeep knowledge of hierarchical floor-planning and networkingAbility to collaborate with cross-functional engineering teams
Score: 85/100 AI verified analysis

About the job

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking an exceptional Senior-level SoC Physical Design Engineer to drive top-level implementation of our complex AI and CPU SoC designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Ft. Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

  • A seasoned physical design engineer who thrives on complex, full-chip implementation challenges.
  • Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams.
  • Passionate about optimizing chip-level implementations for power, performance, and area.
  • Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules

What We Need

  • 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
  • Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
  • Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
  • Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.

What You Will Learn

  • How to implement cutting-edge AI accelerators and high-performance CPUs at the SOC level.
  • Advanced techniques for chiplet integration and next-generation packaging co-design.
  • Strategies for optimizing massive designs with complex power domains and clock architectures.
  • Methods for driving successful chip-level closure through effective cross-functional collaboration.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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