Physical Design Engineer - VLSI & SoC
Content + Source + Freshness • 16 Dec 2025 • 95% confidence
Offer value
Very high value due to the exceptional salary range, involvement in advanced VLSI design, and contribution to innovative satellite technologies.
- Salary of £68,000 - £78,000/hour
- Work on innovative satellite SoCs and cutting-edge VLSI technology
- Significant career growth and training opportunities
- Requires extensive knowledge of specific engineering disciplines
Pros
- Highly competitive salary range (£68,000 - £78,000/hour) for specialized roles
- Opportunity to work on next-gen satellite SoCs and VLSI design projects
- Strong company support for professional development and skill enhancement
Cons
- Extremely high qualifications required (experience in specific EDA tools and deep sub-micron technology)
- Project-related pressures may lead to intensive working hours
- Roles may not offer extensive remote working options due to team collaboration needs
Who it's for
Senior / Expert • Collaborative project-based environment
Good fit
- Senior physical design engineers
- Experts in VLSI and SoC design
- High-achieving professionals seeking impactful projects
Not recommended for
- Individuals without substantial experience in physical design
- Entry-level engineers not ready for high tech challenges
- Candidates preferring loose project restraints and partial roles
Motivation fit
Key skills
About the job
Join a multi-national Physical Design team as a Physical Design Engineer - VLSI & SoC contributing to the development of state-of-the-art Satellite SoCs, from design to production. Work on chips with complex digital and analog modules, including next-generation radiation-hardened satellite modems, using leading-edge EDA tools and process technologies.
Key Responsibilities:
- Physical implementation of complex SoCs and VLSI devices, integrating custom and 3rd-party IP.
- Full block-level timing closure and manufacturing checks, including power planning and analysis.
- Collaborate with Logic Design RTL team to develop timing constraints at block and chip level.
- Insert DFT test structures and support chip-level integration, capture, and simulation.
- Contribute to process improvements and career development initiatives.
Experience:
- BSc in Electrical Engineering, Computer Science, or related field.
- Strong commercial experience in physical design engineering (ASIC/SoC).
- Deep knowledge of COT/ASIC design flows: synthesis, floor-planning, P&R, CTS, STA, timing closure, physical verification, power analysis, DFT/ATPG.
- Experience with deep sub-micron processes (28nm or below).
- Proficiency in scripting languages (Tcl, Python, Perl) and EDA tools (Cadence or Synopsys).
- Strong problem-solving, analytical, and collaboration skills.
- Experience interfacing with design teams, IP/library suppliers, and EDA vendors.
Bluestream People are an Equal Opportunities Employer and operates as an Employment Agency for permanent recruitment and an as an Employment Business for temporary / contract recruitment.
