Senior Design Verification Engineer
Content + Source + Freshness • 17 Dec 2025 • 95% confidence
Offer value
High value due to work within an experienced team focusing on complex CPU verification tasks, offering strong professional growth opportunities.
- Engage in complex CPU verification with industry experts
- High potential for professional development in a startup
- Opportunity to take significant ownership of verification areas
Pros
- Opportunity to work with industry veterans on high-performance CPU designs
- Hands-on responsibility over multiple verification areas
- Strong emphasis on collaboration across engineering disciplines
Cons
- Potentially high pressure to meet deadlines
- Expectations for detailed knowledge can be intensive
- Startup uncertainties may create an unpredictable work environment
Who it's for
Senior • In-office / Hybrid
Good fit
- Verification engineers with experience in CPU architecture
- Candidates seeking impactful roles in cutting-edge projects
- Professionals eager to collaborate cross-functionally
Not recommended for
- Less experienced engineers or new graduates
- Individuals preferring non-technical roles
- Candidates looking for a structured corporate environment
Motivation fit
Key skills
About the job
Senior Design Verification Engineer
Join and be part of an exciting startup in the semiconductor space!
We are a well-funded early-stage startup doing processor design.
The company was founded by industry veterans from Broadcom/Marvell/Sun Microsystems/Intel, who have taken multiple successful high-performance CPUs to tape-out and production.
If you have a strong background in processors, great problem-solving skills, an eye for detail, and a can- do attitude, reach out to us, to explore opportunities.
For this position, we are looking for:
- Strong background in unit/cluster-level verification, of a complex CPU or Cache Coherent sub- system
- Processor architecture (such RiscV, ARM, Mips, Solaris, x86) or Cache coherency experience, and experience in previous processor verification is a plus.
- Strong programming background in System Verilog or C++. UVM experience desirable.
- Good knowledge of assembly or C-programming a plus
You will be working with a small close-knit team and own 1 or more areas of verification.
As a DV engineer you will also be interacting with Architecture, and RTL design closely.
This is a great opportunity to join an early-stage startup and work on exciting designs with significant responsibility.
