ASIC RTL Engineer III, Silicon IP/Subsystem
Content + Source + Freshness • 14 Dec 2025 • 95% confidence
Offer value
High value due to the reputable employer, progressive work environment, and emphasis on collaborative innovation.
- Opportunity to work on advanced silicon solutions at Google
- Potential for career advancement and innovation development
- Collaborate with diverse teams on meaningful projects
Pros
- Contribution to groundbreaking technology products at Google
- Collaboration with multi-faceted teams enhances learning
- Involved in the integration of advanced silicon solutions
Cons
- Expectations and competition may be high
- Potentially unclear compensation information
- Bengaluru’s tech scene may have high living costs
Who it's for
Mid to Senior • On-site
Good fit
- Experienced ASIC and RTL engineers
- Professionals wanting to innovate in hardware processes
- Candidates eager to work in a collaborative environment
Not recommended for
- Entry-level applicants without relevant experience
- Individuals seeking remote positions only
- Candidates who struggle in high-demand environments
Motivation fit
Key skills
About the job
ASIC RTL Engineer III, Silicon IP/Subsystem
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Mid
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
- 3 years of experience in ASIC design flows and methodologies, IP integration (e.g., subsystems, memories, IO's and Analog IP) and RTL design.
- Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience working on memory controller/direct memory access (DMA).
- Experience with industry standard ASIC design tools for RTL lint, VCS, Verdi.
- Experience in AI accelerator design, data-path design.
- Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will own System Verilog implementation, lead PPA (Power, Performance, Area) optimization experiments early on, and collaborate across the verification and physical design teams.
The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Responsibilities
- Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
- Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
- Participate in test plan and coverage analysis of the block and ASIC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
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