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Careers at Google
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ASIC Engineer, IP Design, Silicon

$156,000 - $229,000/year
28 Apr 2025
Mountain View, CA, USA
Verified by Turrior

Content + Source + Freshness • 14 Dec 2025 • 95% confidence

85 / 100

Offer value

High offer score attributed to strong brand recognition (Google) and competitive salary, especially for those passionate about IP design in silicon.

  • Strong salary $156,000–$229,000/year
  • Impactful work on Google's products
  • Collaborative team environment
  • Competitive entry requirements
Pros
  • Salary range ($156,000–$229,000/year) reflects expertise and high demand
  • Opportunity to work on innovative consumer products
  • Team collaboration that drives forward technology
Cons
  • Potentially high workload with tight deadlines
  • Expectations for high-level skill from the start
  • Possibility of limited flexibility in work arrangements

Who it's for

Mid to Senior • On-site or Hybrid

Good fit
  • Mid to senior-level ASIC designers
  • Technical professionals with IP design experience
  • Candidates eager to shape technology products
Not recommended for
  • Entry-level applicants
  • Professionals seeking non-technical roles
  • Individuals preferring isolated work settings

Motivation fit

Desire to push boundaries of hardware designInterest in contributing to products used by millionsWillingness to embrace challenges in tech advancement

Key skills

RTL design with SystemVerilogScripting for automationExperience with ASIC methodologiesEffective communication with multi-disciplinary teams
Score: 85/100 AI verified analysis

About the job

ASIC Engineer, IP Design, Silicon

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corporate_fareGoogleplaceMountain View, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
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Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
  • Experience with a scripting language like Python or Perl.
  • Experience with ARM-based SoCs, interconnects and ASIC methodology.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • 8 years of industry experience with IP design.
  • Experience with methodologies for low power estimation, timing closure, synthesis.
  • Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

  • Define microarchitecture details, block diagrams, data flow, pipelines, etc.
  • Perform RTL development (SystemVerilog), debug functional/performance simulations.
  • Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.
  • Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
  • Communicate and work with multi-disciplined and multi-site teams.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

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