Verification Engineer
Content + Source + Freshness • 12 Dec 2025 • 95% confidence
Offer value
Moderate value due to necessary skill specificity and onsite requirement, balanced by competitive compensation.
- Competitive salary: $66.43–$71.43/hour
- Focus on unique verification methodologies
- Potential hybrid work after trial phase
- Requires experience in a specific technical domain
Pros
- Competitive hourly rate ($66.43–$71.43) for a specialist role
- Significant opportunities for hands-on experience in ASIC and FPGA verification
- Potential for hybrid work model after initial onsite period
Cons
- Initial requirement for full onsite presence may deter some candidates
- Highly specialized skill set may limit applicant pool
- Intensive focus on verification may be less appealing for some engineers
Who it's for
Mid-Level / Senior • Onsite with potential hybrid options
Good fit
- Mid-level verification engineers
- Engineers experienced in SystemVerilog and ASICs
- Professionals seeking growth in ASIC/FPGA technologies
Not recommended for
- Entry-level engineers without relevant experience
- Candidates desiring full remote work options
- Individuals unfamiliar with verification processes
Motivation fit
Key skills
About the job
Description:
Essential skills:
Must be fluent in the synthesizable constructs of SystemVerilog; should be able to design a basic module without any trouble
Must be competent in class-based verification techniques using SystemVerilog; UVM experience is highly preferred, but other frameworks like VMM, OVM, or something custom are still valuable
Must be familiar with how to compile and run a simulation, open a design, and debug it using an industry standard simulator like Synopsys’ VCS, Siemens QuestaSim, or Cadence Xcelium
Must have a good understanding of the industry landscape; should understand and articulate ASIC and FPGA-relevant concepts
Must be able to pick up new techniques quickly and be a strong self-learner; candidate should be able to design new features thoughtfully after considering all tradeoffs with guidance from senior engineers
Nice-to-have skills:
FPGA Experience (Xilinx FPGA preferred), Vivado experience
Write scripts quickly for task automation or result summaries: Python, Bash, Perl, TCL, etc.
High speed IO familiarity like Ethernet, PCIe, CXL
Design creation with client Vivado toolchain; familiarity with various client IPs
Linux kernel debugging experience
Experience with licensed verification IP (VIP) from Siemens, Cadence, or Synopsys
ASIC or FPGA bring-up after chip tapeout
JOB DUTIES:
Participate in design and functional verification of a block(s) of IP. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block and overall system. Be responsible for developing and improving simulation test environments consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally and work within the existing verification infrastructure. Be familiar with hardware modeling and/or assertion-based verification methods.
In this role you will be part of a PCIe development and productization team. A majority of the verification will target PCIe device testing DMA, CXL, IDE, VIP models, traffic generators/checkers, etc.
EXPERIENCE:
3 or more years of verification experience with SystemVerilog for IP or system level verification; a particular focus being deep testbench creation experience and/or agent (AKA BFM) development
Familiar with UVM verification methodologies
Strong debug skills with simulation tools like QuestaSim, VCS, or Xcelium
Strong analytical skills and attention to detail
Excellent written and communication skills
Familiarity with PCIe and serial protocols is a bonus
Xilinx FPGA and tools experience is a bonus
Notes:
100% onsite initially; open to hybrid option after a trial period.
VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status
