Staff/Sr Staff RTL Design Engineer
Content + Source + Freshness • 16 Dec 2025 • 95% confidence
Offer value
High score reflects demand for specialized skills in RTL design, competitive compensation, and opportunities for career advancement in a leading semiconductor company.
- Strong job security with significant market demand for RTL design expertise.
- Involvement in cutting-edge semiconductor projects.
- Career growth in a leading company with innovative culture.
Pros
- Strong demand for RTL design expertise in the semiconductor industry.
- Opportunity to work on innovative SoC designs.
- Potential for career growth in a high-tech company with a solid market position.
Cons
- High expectations and competition among applicants.
- Dependence on project deadlines may affect work-life balance.
- Requires deep technical expertise and collaboration across teams.
Who it's for
Senior / Lead • Remote / telecommute
Good fit
- Senior RTL design engineers with substantial experience.
- Professionals eager to work in high-impact technology projects.
- Collaborative individuals who enjoy problem-solving.
Not recommended for
- Candidates just beginning their careers in engineering.
- Those who do not prefer technical roles with high expectations.
- Individuals desiring a non-technical environment.
Motivation fit
Key skills
About the job
• Micro architect and RTL Design of SoC SubSystem/IP blocks
• Will develop UPF and run CLP checks
• Will be responsible for RTL quality checks - Lint/CDC/LEC
• Create appropriate documentation for hardware blocks
• Responsible for analyse / debug / fixing issues reported by verification team
• Will develop the synthesis constraints for the blocks / subsystem
• Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation
Requirements
- Strong background with multi-year and multi-project experience in RTL SoC Design (Verilog/VHDL), and ASIC/FPGA debug methodologies
- Experience in SerDes PHY, DSP, and Analog mixed signal is desirable
- Knowledge in Ethernet and PCIe standards is desirable
- Proficient in reviewing high-level test plans and coverage metrics.
- Expertise in Design Compiler Synthesis and formal verification using LEC.
- Comprehensive understanding of timing closure.
- Experience in post-silicon bring-up and debugging.
- Team player with strong communication skills to ensure effective program execution.
🔍 ATS Optimization Keywords
Below are skills and terms extracted directly from this job posting to improve Applicant Tracking System (ATS) visibility. This unique feature helps candidates tailor their applications more effectively — a feature exclusive to JobTailor job listings.
Hard Skills
- RTL Design
- Verilog
- VHDL
- ASIC
- FPGA
- Design Compiler Synthesis
- formal verification
- timing closure
- SerDes PHY
- DSP
Soft Skills
- communication skills
- team player
