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Do you want to be at the forefront of innovating the latest hardware designs to propel Microsoft’s cloud growth? Are you seeking a unique career opportunity that combines technical capabilities, cross-team collaboration with business insight and strategy?

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees, we come together with a growth mindset, innovate to empower others, and collaborate to achieve our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Join the Systems Planning and Architecture (SPARC) team within Microsoft’s Azure Hardware Systems and Infrastructure (AHSI) organization, the team behind Microsoft’s expanding Cloud Infrastructure and for powering Microsoft’s “Intelligent Cloud” mission. Microsoft delivers more than 200 online services to more than one billion individuals worldwide, and AHSI is the team behind our expanding cloud infrastructure. We deliver the core infrastructure and foundational technologies for Microsoft's cloud businesses including Microsoft Azure, Bing, MSN, Office 365, OneDrive, Skype, Teams and Xbox Live.

We are looking for a Principal AI Architect to join our team!

Required/minimum qualifications

• Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 9+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 11+ years technical engineering experience OR equivalent experience.
• 10+ years of experience in AI systems, hardware/software co-design, or performance engineering.
• 5+ years of experience in AI accelerator and GPU architectures, including compute pipelines, memory hierarchies, and interconnects.
• 5+ years of experience with PyTorch, CUDA, Triton, or similar frameworks for performance tuning and kernel development.
• 5+ years of experience of cross-disciplinary collaboration between hardware, software, and ML model teams.
• 5+ years of experience in profiling and optimizing large-scale distributed AI workloads.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications

• Experience with compiler and runtime frameworks (e.g., MLIR, TVM, XLA, or custom code generation flows).
• Familiarity with DeepSpeed, Megatron-LM, SGLang, or vLLM training and inference pipelines.
• Deep understanding of transformer-based model architectures and scaling behaviors.
• Hands-on experience with AI performance modeling, benchmarking, or workload simulation.
• Demonstrated technical leadership and communication skills in highly collaborative environments.

Hardware Engineering IC6 - The typical base pay range for this role across the U.S. is USD $163,000 - $296,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $220,800 - $331,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until November 14th, 2025.

#AHSI #SPARC

• Model Bring-Up & Characterization
• Lead the bring-up and functional validation of LLMs on custom AI accelerators and GPUs
• Develop and maintain detailed performance characterizations across compute, memory, and interconnect domains.
• Instrument and profile end-to-end training and inference workloads to identify scaling inefficiencies and performance gaps.
• Hardware/Software/Model Co-Design
• Partner with silicon and system architects, compiler/runtime engineers, and model researchers to define co-design strategies that maximize efficiency and utilization.
• Drive studies and experiments across quantization formats, tensor parallelism, activation checkpointing, memory layouts, and communication topologies.
• Performance Optimization-Analyze kernel- and system-level traces to identify limiting factors in compute, memory, and interconnect.
• Propose and implement optimizations in scheduling, fusion, and data movement to improve throughput and power efficiency.
• Guide runtime and compiler improvements informed by workload analysis.
• Cross-Functional Leadership
• Collaborate with teams across Azure ML, DeepSpeed, and Maia hardware programs to deliver production-grade AI infrastructure
• Present architectural findings and recommendations to senior engineering leadership.
• Mentor and technically guide engineers working in performance, compiler, and system bring-up domains.