Design Verification Engineer
Content + Source + Freshness • 12 Dec 2025 • 95% confidence
Offer value
Moderate value stemming from involvement in cutting-edge satellite technology and the opportunity for innovative contributions.
- Engage in advanced satellite communication technologies
- Hands-on role with ample project collaboration
- Innovative environment in a rapidly evolving field
Pros
- Participation in pioneering technology for satellite communications
- Opportunity for hands-on contributions in verification processes
- Collaboration with teams on advanced technology development
Cons
- Potentially lower compensation compared to other engineering roles
- Niche area may limit marketability outside of satellite technology
- Expectations for rapid development and testing cycles
Who it's for
Mid-level • On-site with some flexible hours
Good fit
- Mid-level engineers specialized in chip design and testing
- Tech enthusiasts interested in satellite communications
- Candidates with a proactive approach to problem-solving
Not recommended for
- Entry-level engineers without relevant project experience
- Those not inclined towards detailed engineering tasks
- Individuals lacking interest in emerging technologies
Motivation fit
Key skills
About the job
Description
Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.
The Role:
Be part of Project Kuiper’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.
In this role you will:
· Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models
· Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
· Participate in the validation of ASIC implementations in Verilog/SystemVerilog
· Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM
· Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
