ASIC/VLSI Design Engineer
Full Time
full-time
6 Nov 2025
Austin
Verified by Turrior
Content + Source + Freshness • 18 Dec 2025 • 95% confidence
78 / 100
Offer value
Moderate offer value due to growth opportunities and engagement with cutting-edge technology, but lacks information on compensation.
- Opportunity to design cutting-edge VLSI communication systems
- Focus on innovative algorithm implementations
- Requires good collaboration skills among teams
- Salary details not specified, limiting overall attractiveness
Pros
- Chance to work on innovative VLSI designs
- Engagement with algorithm and architecture teams
- Solid opportunities for professional growth and skill enhancement
Cons
- Limited information on salary and benefits
- Expectations may vary as the role involves complex interactions
- High level of responsibility may lead to work pressure
Who it's for
Mid-Career • On-site
Good fit
- Experienced engineers in VLSI or ASIC design
- Professionals motivated by collaborative project work
- Candidates passionate about advanced communication systems
Not recommended for
- Entry-level candidates or those with no VLSI experience
- Individuals looking for remote working conditions
- Candidates preferring low-responsibility roles
Motivation fit
Desire to innovate in semiconductor designInterest in participating in dynamic design processesWillingness to adapt to evolving project needs
Key skills
VLSI design and architectureRTL coding with Verilog/SystemVerilogCross-functional team collaborationSynthesis and timing analysis
Score: 78/100 AI verified analysis
About the job
We are looking for talented and experienced VLSI Design Engineers/Micro-architects.As an VLSI Digital Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch.Key Responsibilities for a VLSI Design Engineer:Work closely with Algorithm and Architecture teamsUnderstand and translate high-level algorithmic requirements into efficient hardware implementations.Learn and analyze relevant protocols and standardsInterpret protocol specifications (e.g., Ethernet, etc.) and apply them accurately in design.Participate in all design stages:Micro-architecture definitionRTL coding (using Verilog/SystemVerilog)Synthesis-friendly coding and timing-aware designCollaborate cross-functionally:Verification team: For testbench development, debug support, and functional coverage closure.DFT team: Ensure design is scan-insertable, supports ATPG, BIST, etc.Backend/Physical design team: For floorplanning, timing closure, and routing feedback.Participate in Design ReviewsPresent and defend design decisions in peer and formal reviews.Perform Synthesis and Timing AnalysisGenerate synthesis constraints (SDC), run synthesis, and analyze timing reports.Debug and Fix Functional/Timing IssuesCollaborate in post-silicon or pre-silicon debug; use waveforms, assertions, and logic analyzers.Optimize for Area, Power, and Performance (PPA)Identify bottlenecks and opportunities for improvement within RTL.DocumentationMaintain clear design documentation for reusability and reference (e.g., micro-architecture specs, interface docs).Contribute to IP/SoC IntegrationWork on integrating design blocks into larger systems and handling system-level interfaces.Participate in Silicon Bring-up and Validation (optional but valuable)Support bring-up of first silicon and assist with post-silicon validation, if applicable.Keep up-to-date with Industry Trends and ToolsLearn new EDA tools, languages, and methodologies (e.g., CDC, Linting, Formal Verification).
