ASIC Engineer
Content + Source + Freshness • 14 Dec 2025 • 95% confidence
Offer value
A balanced offer with strong backing from Jane Street, focusing on unique contributions to hardware design and a collaborative tech environment.
- Dynamic hardware engineering at Jane Street
- Influential role in ASIC development projects
- Requires software integration skills
- Salary details not specified
Pros
- Innovative hardware environment at Jane Street
- Chance to influence advanced hardware applications
- Opportunities for continuous learning and adaptation
Cons
- High expectations for software and hardware integration
- Vague salary information may affect expectation management
- Varied project demands may lead to fluctuating workloads
Who it's for
Mid to Senior • On-site
Good fit
- Mid-level ASIC professionals
- Engineers interested in innovative tool usage
- Candidates eager to work on diverse projects
Not recommended for
- New graduates or lack of applicable experience
- Persons who avoid collaborative work environments
- Individuals seeking stability without project variability
Motivation fit
Key skills
About the job
About the Position
We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you’ll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.
We’re big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That’s why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don’t expect you to know OCaml (we’ll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.
About You
- Have practical experience in RTL design and verification
- Experienced in ASIC design using either Synposys or Cadence flows, including at least one of the following:
- Front-end RTL design and synthesis
- Back-end physical design
- Verification (including formal)
- Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.)
If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.
